The present invention relates to high density electronic memory components and packages and, more particularly, to an ultra high density memory package featuring demountable memory chips and integrated thermal management features.
In semiconductor devices, operating efficiency is one of the ultimate benchmarks of performance. Electrical signals are switched on and off relative to a particular voltage level within these devices, resulting in patterns which are considered xe2x80x9cdataxe2x80x9d. One measure of operating efficiency, therefore, is the voltage required to operate the semiconductor device. Because electrical power is proportional to the square of the voltage, the lower the voltage, the less power must be dissipated as heat.
Another benchmark of performance for semiconductor devices is operating speed. In other words, performance gains may be achieved by operating switching devices at increased switching speed, generally referred to as clock rate (i.e., the speed of switching of the electrical signal by which other signals are synchronized). Clock rates, in turn, are dependent on semiconductor fabrication processing techniques. Moreover, increased clock rates generally also result in increased operating temperatures due to the physics of electron motion.
At high clock speeds, signal integrity may be affected largely by the electric noise, due mostly to inductive and capacitive coupling effects that lead to signal reflection, distortion and delay. Inductance and capacitance may be controlled by suitably located ground planes. For example, a stripline configuration or a pin grid array (PGA) connector with grounded pins around the signal pin can be used. More specifically, to reduce signal reflection, the impedance along the signal path must be matched (e.g., to 28 ohms) as is the present practice in most sophisticated circuits on printed circuit boards (PCBs). Also, to control the signal delay, signal path lengths should be matched so that signals to different memory chips arrive in phase (at the same time).
In the area of electronic packaging, high speed semiconductor devices are interconnected one to another by the shortest possible signal path to minimize signal delays and thereby increase overall system performance. Such is the case with memory devices placed near one or more processing or logic units (processors or CPUs).
The amount of memory available to a processor is limited practically, however, by the capacity of the memory device and the density with which multiple memory devices can be stacked together in close proximity to the processor. By increasing both clock frequency and stacking density of the memory chips, system performance may be improved (i.e., speed increased), but with the aforementioned, detrimental result: more heat is generated. The heat problem, as well as the noise problem, are exacerbated by the fact that the heat-generating devices are now packaged in relatively smaller confines. More heat is generated, and the signal quality becomes an issue because of greater concern for signal noise and delays as clock/bus speeds increase.
Therefore, it is the goal of high performance package designs to maximize packing density while providing effective thermal management. Widely accepted practices for achieving these goals are to miniaturize package sizes and thicknesses or profiles. Commonly used forms include thin, small-outline packages (TSOPs), chip-scale packages (CSPs), and chip-on-board (COB) structures. Decreasing package size allows for both shorter signal lengths as well as shorter thermal paths. The chip packages are generally mounted flush and one-high onto a PCB. This layout practice provides the lowest profile, but unfortunately also dictates low packing density.
One implementation of highly dense memory is the dual inline memory module (DIMM). The DIMM is constructed by soldering TSOP devices onto one or both sides of a length of memory circuit board. Electrical contacts along an edge of the circuit board allow mounting the DIMM circuit board in a mating socket, generally perpendicular to the surface of a motherboard. The TSOPs are thereby aligned into a maximum configuration of eight or nine packages on either side of the DIMM, for a total of sixteen to eighteen packages, hard-soldered to the DIMM circuit board.
The relatively long wire bonds of the TSOPs, however, cause high levels of inductance, which results in crosstalk and signal delays. Both crosstalk and signal delays may severely limit performance at high frequencies. While the DIMM itself is socketable, which allows for upgrading when desired, individual TSOP modules require hot rework if a device fails.
DIMMs can be considered natural heat fins, but cooling efficiency is low due to the lack of an effective thermal transfer medium from the die to the air, and the lack of a short air channel in the direction of air flow (i.e., parallel to the motherboard), exacerbated by the size of the DIMM when placed next to another DIMM.
The RAMBUS(copyright) inline memory module (RIMM) is similar to the DIMM. A high density implementation using RIMMs has been proposed by Nippon Electric Company (NEC). The primary advantage of the RIMM implementation over DIMM is that the RIMM has been specifically designed for high frequency operation. In the NEC Concurrent RAMBUS approach, the edge of a thin, edge-leaded package is surface-mounted onto a DIMM-like structure. Many of these edge packages may be mounted in this manner, creating a stack of discrete packages.
While the maximum operating frequency of DIMM modules has been limited to relatively low frequencies, a RIMM module may be operated at much higher speeds to be compatible with the high CPU operating speeds currently employed in leading edge workstations and servers. However, inherent deficiencies in the present RIMM implementation do not allow for impedance matching memory chips to the memory bus, effectively controlling noise, or controlling signal propagation delay.
Soldered connections are limited by processing conditions of surface mount devices. The edge leads require relatively large interlead spacing to allow reliable soldering to the board. While an intermediate interconnect layer is not present (the pad serves as the interconnect), it is still necessary to mount (reflow) all of the devices simultaneously. The structure does not provide an adequate thermal solution because it does not allow for efficient airflow or thermal dissipation. Neither does it allow for simple rework, as the small intermodule spacing complicates processes for applying heat in order to rework the vertical package.
U.S. Pat. No. 5,572,065 for HERMETICALLY SEALED CERAMIC INTEGRATED CIRCUIT HEAT DISSIPATING PACKAGE; issued Nov. 5, 1999 to Carmen D. Burns, describes methods by which packages similar in form to TSOPs can be fabricated and mounted atop one another to achieve higher packing density and to dissipate heat. Designs such as described by Burns show that a silicon chip can be lapped thin, stacked on a thermally conductive lead frame, and electrically connected with rails at common sites, resulting in a stacked package that can be permanently bonded to a PCB (i.e., a motherboard or an add-on board). While such an approach can pack chips at a higher density, it results in a packaging structure inherently expensive and difficult to rework, should any portion of the aggregate device fail to work properly. The primary means for heat removal is inefficient and relies on thermal conduction through the body of the stack into a thermal slug or sink. Most importantly, these stacked memory devices cannot easily or inexpensively be adapted for high frequency operation which would require controlling electrical noise, impedance matching and signal delay matching (skew minimization).
In contradistinction, the high density circuit package of the present invention provides both an extremely high packaging density and efficient thermal management structure. The high density package allows short interconnection lengths both within a module and among modules in the package and to the card or board onto which the module is connected. The inventive connector permits signal lines leaving and entering the package to be disposed extremely close together.
U.S. Pat. No. 5,367,766 for ULTRA HIGH DENSITY INTEGRATED CIRCUIT PACKAGES METHOD; issued Nov. 29, 1994 to Carmen D. Burns, et al., discloses an integrated circuit package whose conduction rails also function as heat fin structures to radiate heat generated within the package. However, the limited contact area of the fins with the thermal paths precludes effective convective heat transfer.
On the other hand, the thermal management structures of the inventive package are designed to optimize both thermal conduction and radiation, allowing for maximum circuit density without heat build-up, which could degrade module performance.
In U.S. Pat. No. 5,566,051; issued Oct. 15, 1996 to Carmen D. Burns, a lead frame itself is utilized as a thermal structure that can be placed in contact with a heat sink. This design also suffers from a limited thermal path, further interrupted by perforations in the frame that are necessary to reduce thermal stress.
The thermal structures of the inventive package provide both thermal paths and radiating surfaces, which are optimized for both thermal conduction and radiation, permitting maximum circuit density while controlling heat build-up in the module.
None of the aforementioned prior art structures provides for high frequency operation with structures such as signal lines, ground planes, dielectrics, connectors, etc. specifically included to reduce signal noise and delay, or to control signal path impedance. Neither do these prior art structures provide for reliable thermal management of a stacked, integrated circuit module because they each require a second level of interconnect between the singular devices making up the module stack and the PCB on which the stack is mounted. Variations or flaws in the intermediate interconnect layer may drastically affect electrical and mechanical reliability as more devices are added to the stack.
In addition, efficient and effective thermal conduction becomes even more crucial as heat is added to the stacked system, which already has narrow thermal paths. The final stack structure requires hot processing temperatures and extremely careful techniques, making both assembly and rework very expensive.
Nothing in the aforementioned prior art references or any other prior art known to the present inventors is seen to teach or suggest the high-density, thermally-managed packaging structure of the instant invention.
It is, therefore, an object of the invention to provide an extremely high density module interconnection package.
It is another object of the invention to provide a memory module optimized for high frequency operation with specific structures for controlling impedance, controlling signal delays and reducing electrical noise.
It is a further object of the invention to provide a packaging structure having integrated thermal management structure to effectively maintain a reasonable operating temperature within the packaging structure.
It is yet another object of the invention to provide such a packaging structure with integrated thermal management in a low profile configuration.
It is an additional object of the invention to provide a high density module packaging structure wherein individual modules may be temporarily interconnected for testing.
It is yet another object of the invention to provide a high density module package wherein individual modules may be permanently interconnected after testing indicates that all modules are functional.
It is still another object of the invention to provide a high density circuit module package wherein module rework may be easily and inexpensively performed without excessive exposure of modules to damage by heat or handling during rework.
It is yet another object of the invention to provide a high density circuit module package wherein electrical connectors both on daughter cards within the module and external to the module minimize electrical inductance to provide stable high frequency performance.
The present invention features an ultra high density, three-dimensional electronic circuit package suitable for constructing high capacity, high speed computer memory cards and the like. A high density connector system allows narrow contact-to-contact spacing, thereby permitting more discrete electrical connections within a given space than have heretofore been available. The small physical size of the contact system minimizes inductance and crosstalk, both on daughter cards carrying the memory devices as well as on the memory board, thus making the inventive packaging system suitable for high speed/high frequency applications. In particular, the daughter cards carrying the actual memory devices may be equipped with structures such as ground planes, etc. to minimize electrical noise and control impedances, thereby maintaining signal synchronization (i.e., controlling skew). In addition, the novel, demountable contact system allows easy test and/or burn-in.
A memory card has a number of electrical receptacles adapted to receive a daughter card. The daughter card has memory devices attached to it and a corresponding number of electrical connectors placed along at least one edge, adapted to detachably mate with the electrical receptacles of the memory card. These electrical connectors play a critical role in the high frequency-optimized design wherein impedance is controlled and electrical noise minimized. The demountable connectors also allow easy rework of the module before optional, permanent solder attach.
A number of implementations are disclosed that minimize packing space, while maximizing thermal efficiency. The inventive module may accommodate bare dies or variations of thin packages such as TSOPs, CSPs, COBs, etc., described hereinabove and/or well known to those skilled in the circuit packaging art. These dies or packages are mounted onto daughter cards, which in turn are mounted onto either a motherboard or memory card using pin/hole technology.